1. Field of the Invention
This invention relates generally to integrated circuits, and, more particularly, to an adjustable high-trigger-voltage ESD protection device.
2. Description of the Related Art
Electrostatic discharge (ESD) is a known phenomenon capable of destroying integrated circuits. In ESD, a relatively large pulse of current, originating from an outside source, is delivered unintendedly to elements of an integrated circuit (IC). One outside source of ESD is the human body. The human body is capable of storing and then discharging energy. The human body may on certain occasions charge to 20 kV simply through ordinary movement such as walking over a carpet. Other objects such as solder irons and printed circuit boards are also capable of storing and then discharging energy. Electrostatic discharge may destroy an IC when a relatively large amount of stored energy discharges in a relatively short amount of time into the IC through a conductive path established when the IC comes into contact with a charged person or object.
Although a variety of integrated devices may be susceptible to damage from an ESD vent, metal oxide semiconductors (MOS) are particularly susceptible due to the low voltages required to cause damage to the gate oxide. An ESD pulse supplied to a MOS transistor through the gate may break down the dielectric gate oxide barrier between the gate and the channel, which may lead to permanent damage by leaving a conductive path of ionized dielectric or trapped electrons, or by burning a hole in the gate oxide. The possible results of an ESD event include crippling the device functionality, decreasing the device life cycle, or destroying the device.
FIG. 1A illustrates a block diagram of a conventional integrated circuit device 20. The integrated circuit device 20 includes internal circuit components 22 and an external bond pad 24. The external bond pad 24 facilitates interfacing the integrated circuit device 20 with other electrical components (not shown). In the integrated circuit device 20 shown in FIG. 1A, the external bond pad 24 functions as an input pad. An input buffer 25 is coupled between the external bond pad 24 and the internal circuit components 22. The integrated circuit device 20 also includes an ESD protection device 26 coupled to the external bond pad 24, which protects the internal circuit components 22, the external bond pad 24, and input buffer 25 by reducing or eliminating the effects of an ESD event.
It is well known in the industry that the ESD protection device 26 may have many different embodiments. FIG. 1B illustrates a cross-sectional view of a field device 30 used as the ESD protection device 26 in FIG. 1A. The field device 30 includes drain, source, and gate terminals 32, 34, 36. In addition, the field device 30 includes a substrate 37. Typically, the external bond pad 24 is coupled to the drain terminal 32 of the field device 30, and the source and gate terminals 34, 36 are coupled to a ground node 38 or to a power supply node (not shown). The field device 30 remains "off" (i.e., does not conduct current) until a sufficiently large pulse of current (e.g., an ESD event) is applied to the terminal of the external bond pad 24. The field device 30 switches "on" (i.e., begins to conduct current) once the voltage of the external bond pad 24 increases, from an external event, beyond the reverse-bias breakdown voltage of the field device 30. The reverse-bias breakdown voltage, also known as the trigger voltage or breakover voltage, is the voltage necessary to establish a conductive path between the source and drain terminals 34, 32 through the substrate 37 of the field device 30.
FIGS. 2 and 3 are illustrative embodiments of a pn junction, which are representative of the pn junction between the drain terminal 32 and the substrate 37 of the field device 30 shown in FIG. 1B. Those of ordinary skill in the art will appreciate that FIGS. 2 and 3 are models of a semiconductor device useful as an aid in the understanding of the breakover voltage of the field device 30 shown in FIG. 1B.
Those of ordinary skill in the art will appreciate that semiconductor material may be made either N-type or P-type by doping the semiconductor material with the appropriate dopant material (e.g, boron, phosphorous, etc.) Furthermore, in order to aid in the illustrations, the semiconductor material may be labeled with a p (P-type doping) or with an n (N-type doping.) In addition, the semiconductor material may be heavily doped, denoted with a "+", or lightly doped, denoted with a "-".
FIG. 2 shows a generalized pn junction 40 with a reverse-bias voltage applied to the terminals 41, 42 of the pn junction 40. The pn junction 40 includes a lightly doped n-type material 43 (denoted with an n-) and a lightly doped p-type material 44 (denoted with a p-). The center of the pn junction is marked by a centerline 46.
Because of the charges associated with the n-type and p-type material 43, 44, a space charge region 48 exists in the center of the pn junction 40. The space charge region 48 includes a first boundary 50 that extends partially into the n-type material 43 and a second boundary 52 that extends partially into the p-type material 44. The first boundary 50 of the space charge region 48 is positively charged, and the second boundary 52 is negatively charged. The charge of the first and second boundaries 50, 52 results in a potential difference across the space charge region 48, hence, an electric field is produced across the space charge region 48.
Initially, the width of the space charge region 48 is a function of the doping concentrations of the n-type and p-type materials 43, 44 of the pn junction 40 (i.e., the width of the space charge region 48 depends on the charge concentration of the n-type and p-type materials 43, 44). As the reverse-bias voltage applied to the terminals 41, 42 of the pn junction 40 increases, the first and second boundaries 50, 52 of the space charge region 48 extend further into the n-type and p-type materials 43, 44 away from the divider 46, which is illustrated by positions 54 and 56 in FIG. 2. Because the doping concentrations of the n-type and p-type material 43, 44 are approximately equal, the space charge region 48 widens in a substantially symmetric manner, as shown in FIG. 2.
The width of the space charge region 48 continues to expand as the reverse-bias voltage applied to the terminals 41, 42 of the pn junction 40 increases. In addition, the electric field continues across the extended space charge region 48, and the electric field intensifies as the reverse-bias voltage increases. Eventually, the reverse-bias voltage reaches the breakdown voltage (e.g., 30-50V) of the lightly doped pn junction 40. At the breakdown voltage, the intensity of the electric field reaches a critical value and current begins to flow between the terminals 41, 42 across the pn junction 40.
FIG. 3 is an illustrative embodiment of the pn junction formed between the substrate 37 and the drain 32 of the field device 30. A reverse-bias voltage is applied to the external bond pad 24. The center of the pn junction 60 is marked by a centerline 62.
Because of the more heavily doped drain 32, a space charge region 64 is not symmetrically disposed about the centerline 62, but extends predominately into the lightly doped substrate 37, as shown in FIG. 3. A first boundary 66 of the space charge region 64 is essentially pinned by the heavily doped drain 32 and resides relatively close to the centerline 62 of the pn junction. A second boundary 68 is located in the lightly doped substrate 37. Because the first boundary 66 of the space charge region 64 is essentially pinned by the heavily doped drain 32, increasing the reverse-bias voltage results in the space charge region 64 expanding predominately into the substrate 37, which is illustrated by positions 70 and 72 in FIG. 3 (i.e., any increase in reverse-bias voltage will result in a substantially asymmetric widening of the space charge region 64).
The width of the space charge region 64 will continue to expand as the reverse-bias voltage applied to the external bond pad 24 increases. In addition, the electric field continues across the extended space charge region 64, and the electric field intensifies as the reverse-bias voltage increases. Because the heavily doped drain 32 essentially pins the first boundary 66, the space charge region 64 widens at a reduced rate, thus, the electric field reaches a critical value at a lower reverse-bias voltage, consequently, resulting in a lower breakdown voltage (e.g., 10-12V).
Typically, the ESD protection device 26 (shown in FIG. 1A) dissipates an ESD pulse through snapback, a phenomenon well known to those skilled in the art. FIG. 4 illustrates the current (I) versus voltage (V) characteristics of a typical ESD protection device operating in a snapback mode. The breakover voltage (Vbv), also known as the trigger voltage or reverse-bias breakdown voltage, is the voltage at which the ESD protection device switches "on" (i.e., begins to conduct current). Once the voltage applied to the external bond pad 24 reaches the breakover voltage (Vbv) conduction begins, and the voltage of the external bond pad 24 decreases to a value known as the snapback voltage (Vsb). Increases in the voltage of the external bond pad 24 above the snapback voltage (Vsb) after snapback has occurred results in relatively large increases in current, as shown in FIG. 4 by the steep upward slope of the graph above a inflection point 74 at Vsb.
By operating in a snapback mode, the ESD protection device 26 (shown in FIG. 1A) decreases the voltage of the input buffer 25 to Vsb, consequently, protecting the external bond bad 24 from excessive voltages. In addition, because snapback reduces the voltage of the external bond pad 24 to Vsb, the power dissipated through the ESD protection device decreases during an ESD event, and the ESD pulse may be safely dissipated without destroying the ESD protection device 26.
The prior art method, however, suffers from at least one shortcoming in that the ESD protection device 26 of FIGS. 1A and 1B shunts any signal with a voltage greater in magnitude than the reverse-bias breakdown voltage. Certain integrated circuit devices include programming pins that require a high voltage (e.g., 20V) to program devices, such as anti-fuses, within the device. The programming voltage is typically greater than the reverse-bias breakdown voltage of standard ESD protection devices, making them unusable. The ESD protection circuit 20 of FIG. 1A may switch "on" prematurely when used in conjunction with the high voltage programming pins, and prevent the programming from being accomplished. Thus, the circuit of FIG. 1A is unsuitable for protecting high voltage programming pins.
The breakover voltage for the field device 30 of FIG. 1B is slightly tunable by varying process parameters, such as doping levels. However, because programming voltages for devices may vary, it would be desirable to have an ESD protection device that has a highly adjustable breakover voltage.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.